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ZL9117M
Typical Application - Single Module
330μF
2X22μF
V IN
BULK
CERAMIC
4.5 to 13.2V
C 1
+
C 2
VIN
VR
C 5
4.7μF
10μF
CERAMIC
V DD
C 3
V LOGIC 10k Ω 10k Ω 4.75k Ω
C 6
C 7
C 8
4.5 to 13.2V
V DRV CERAMIC
4.5 to 6.5V
3.0 to 6.0V
CERAMIC
R 1 R 2 R 3
10μF
C 4
VDD
VDRV
ZL9117M
V25
VOUT
4.7μF
CERAMIC
4X100μF 2x330μF
CERAMIC POSCAP
+
V OUT
1.2V 17A
SCL
SDA
SCL
SDA
DDC
EN
VTRK
SYNC
DDC
EN
VTRK
SYNC
R SA = 51.1k Ω
SMBUS ADD = 0X2A
R SET = 31.6k Ω
V OUT = 1.2V
FB-
FB+
R 4 = 200 Ω
NOTES:
4. R 1 and R 2 are not required if the PMBus host already has I 2 C pull-up resistors.
5. Only one R 3 per DDC bus is required when DDC bus is shared with other modules.
6. The VR, V25, VDRV, and VDD capacitors should be placed no farther than 0.5cm from the pin.
7. R 4 is optional but recommended to sink possible ~100μA backflow current from the FB+ pin. Backflow current is present only when the module is
in a disabled state with power still available at the V DD pin.
8. When Low-Side power FET is selected to be enabled as a response to an OV fault, it is recommended to place a Schottky diode close to the VOUT and
PGND pins in order to prevent voltage at the FB+ pin dropping below absolute minimum of -0.3V, which may be caused by negative current build up
on the internal power inductor.
5
FN7914.3
July 22, 2013
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